FIG. 1 is a construction diagram illustrating a conventional circuit for generating a variety of control signals, i.e., many kinds of precharge signals or active signals, which are used for accessing data in semiconductor memory elements.
In static RAM (SRAM) technology, there is a technique known as address-transition detection (ADT). In ADT, a change in the address input is sensed so that the bit lines that will be effected can be equilibrated sooner. In the construction of FIG. 1, a coupling part 10 and a clock generating part 20, which are shown in a dotted line, generate reference clocks of the control signals for controlling operations of the memory elements according to the ADT technique.
FIG. 2 is a construction diagram illustrating a reference clock generating circuit according to the conventional art. Referring to FIG. 2, there are provided the coupling part 10 and the clock generating part 20. The clock generating part 20 develops a one-shot pulse in response to the detection of an address transition. This pulse is used to activate the bit line equilibration, and optionally the bit line pre-charge as well. The coupling part 10 includes a plurality of NMOS transistors MN1.about.MNn. The clock generating part 10 includes a delay circuit 21, a first PMOS transistor MP1, a second PMOS transistor MP2, and an inverter INV.
The plurality of NMOS transistors MN1.about.MNn in the coupling part 10 act as output transistors for the n address change detecting parts. The plurality of NMOS transistors MN1.about.MNn are turned on/off according to a corresponding plurality of detection signals ATDi outputted from a plurality of address change detecting parts of FIG. 1, the signals ATD, changing according to changes in address data. Further, when turned on, the plurality of NMOS transistors MN1.about.MNn maintain the potential of their drain terminals at the same level as that of their source terminals, i.e., they pull the line ATCOM down to VSS. The delay circuit 21 has inputted to it a potential on a common bus ATCOM and delays the potential for a predetermined time before outputting it.
The first PMOS transistor MP1, on whose gate terminal is inputted an output signal VG of the delay circuit 21, is turned on when the output signal VG is at the low level, and transmits a predetermined positive voltage VCC to the common bus ATCOM connected with its drain terminal, the positive voltage VCC being inputted to its source terminal. Then, the first PMOS transistor MP1 pulls-up the common bus ATCOM. The second PMOS transistor MP2 maintains the common bus ATCOM at the high level during a stable state. The inverter INV has inputted to it the potential on the common bus ATCOM and outputs the inverted potential to drive a load (not shown) connected to its output terminal ATDSUM.
The above constructions are designed to synchronize an internal signal by generating the short pulse according to the output signal from the change detecting part in the memory to be asynchronously driven. At this time, a change detecting part should be associated with each input buffer of the inputted address data.
In operations with reference to FIG. 2, the outputs ATD of the change detecting part drive the common bus ATCOM by the coupling part 10. The coupling part 10 uses a tree type OR-gate or a wired OR-gate structure, the latter being depicted in FIG. 2.
FIGS. 3A-3D depict wave forms for the main parts of the circuit of FIG. 2 during its normal operation. FIGS. 4A-4D depict waveforms for the main parts of the circuit of FIG. 2 during its abnormal operation. Referring to FIGS. 3 and 4, the following describes operation of the circuit for generating the control signals which are used for accessing the data of the semiconductor memory elements.
In the case that the memory is at a static state, the common bus ATCOM is raised to the high level by the always-on second PMOS transistor MP2. At this time, since the output ATDi of the change detecting part is at the low level, the NMOS transistors MN1.about.MNn for a pull-down operation are turned off. The output signal VG of the delay circuit 21 is the high level, so the first PMOS transistor MP1 is also turned off. Therefore, the output ATDSUM is maintained at the low level.
If a change arises in the i-th address of the address signals inputted from the outside, and an output ATDi of the i-th change detecting part is thereby changed to the high level (see FIG. 3A), the NMOS transistor MNi is turned on and the common bus ATCOM is thus changed to the low level (see FIG. 3B). At this point, the second PMOS transistor MP2 having a large resistance value is not intended to have influence on a level change of the common bus ATCOM. Thereafter, if the output ATDi of the i-th change detecting part is changed to the low level, the common bus ATCOM is maintained at the low level as a floating state.
At this moment, if the signal from the delay circuit 21 is applied to the gate terminal of the first PMOS transistor MP1, i.e., a signal VP inputted to the gate terminal of the first PMOS transistor MP1 is at the low level (see FIG. 3C), the first PMOS transistor MP1 is turned on and the common bus ATCOM is thus changed to the high level (see FIG. 3B).
Therefore, pulse width of the output signal ATDSUM of the inverter INV is the same as a delay time of the delay circuit 21 (see FIG. 3D).
Further, when the memory is operated or the memory is at the static state, the short pulse can be applied, as noise, to an address input terminal of the memory by an external system. Furthermore, in the case that a large current flows during the output change of the memory, noise may be generated in the internal power bus of the memory, and the noise may be thus feed-back to the input buffer. Accordingly, the change detecting part should be included with the address buffer. Moreover, the address buffer and the change detecting part are included in FIG. 1 so that the short pulse outputted therefrom can drive the coupling part shown in FIG. 2. Through such an operation, if the common bus ATCOM falls to the low level, i.e., a ground voltage VSS, the delay circuit 21 turns on the first PMOS transistor MP1. Thereby, an output of a normal state is made.
However, in case that the pulse width of the signal ATD outputted from the change detecting part is narrow (see FIG. 4A), the NMOS transistors MN1.about.MNn turned on or turned off by the signal ATD don't have much operating time. Thus, the common bus ATCOM is not pulled down enough. Thereby, the potential of the common bus ATCOM can be maintained at a level between the positive voltage VCC and the ground voltage VSS (see FIG. 4B).
In this case, since the delay circuit 21 does not operate, the common bus ATCOM is pulled-up by the second PMOS transistor MP2. That is, as shown in FIG. 4C, since the output signal of the delay circuit 21 is not accurate, the potential of the common bus ATCOM is at the abnormal state. Thus, the output signal ATDSUM of the inverter INV which is used for reversely outputting the potential of the common bus ATCOM is generated as the short pulse or is shown in an abnormal form (see FIG. 4D).
The feature, as shown in FIG. 4, is needed in a reading operation of the memory. However, such feature can generate a malfunction in the memory in view of a fact that sequence of a signal should be appropriate for timing.
In case of using the coupling circuit according to the conventional art, it is difficult to prevent the clock signal ATDSUM from being generated as a short pulse.